1. Field of the Invention
The present invention generally relates to a nonvolatile ferroelectric memory device having a hierarchical bit line architecture, and more specifically, to a nonvolatile ferroelectric memory device comprising a sense amplifier array for sensing cell data without using a reference voltage and pulling down a precharge voltage level of a data bus to a predetermined level before data are sensed to improve transmission characteristics of cell data, and a data sensing method using the same.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
The technical contents on the above FeRAM are disclosed in the Korean Patent Application No. 1998-14400 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FeRAM are not described herein.
As the chip operation voltage of the FeRAM becomes lower, the cell sensing voltage also decreases. As a result, it is difficult to embody the rapid operating speed in a FeRAM chip having a 1T1C (1-Transistor 1-Capacitor) structure. Specifically, when the sensing voltage of cell data is small, it is difficult to sense cell data due to the small voltage margin.